1. Technical Field
The present disclosure relates to a package method and a package structure and, more particularly, to a method and a package structure for wafer level packaging.
2. Background
In the through silicon via (TSV) technique and a copper electroplating process, the current silicon interposer acts as an interface, which is electrically coupled between an upper surface of the interposer and a bottom surface of the interposer. Because a diameter of a hole fabricated by the TSV technique is smaller than a conventional hole, it has great difficulty forming a conducting trace in the through hole by using the copper electroplating process. Even if the copper electroplating process is completed, the silicon interposer is required to be grounded so as to create an electrical connection between the upper surface and the bottom surface thereof; hence, the yield rate may be decreased due to the grinding operation. Moreover, in the copper electroplating process, the electroplating solution and device are therefore required to be rearranged and redesigned such that the cost, including the redesign and manufacturing of the device, will be increased.